/*
 * @Author: Laputa
 * @Version: V0.1
 * @Date: 2023-07-11 16:30:23
 * @LastEditors: Laputa
 * @LastEditTime: 2023-09-15 16:45:19
 * @Description: This file contains the functions prototypes for the DMA firmware library.
 *
 * Copyright (c) 2023 by Levetop, All Rights Reserved.
 */

#ifndef _LT168_DMA_H
#define _LT168_DMA_H

#include "LT168.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/

/* DMA CR */
#define DMA_CR_EDBG_MASK                        (0x2U)
#define DMA_CR_EDBG_SHIFT                       (1U)
#define DMA_CR_EDBG(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

#define DMA_CR_ERCA_MASK                        (0x4U)
#define DMA_CR_ERCA_SHIFT                       (2U)
#define DMA_CR_ERCA(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

#define DMA_CR_ERGA_MASK                        (0x8U)
#define DMA_CR_ERGA_SHIFT                       (3U)
#define DMA_CR_ERGA(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

#define DMA_CR_HOE_MASK                         (0x10U)
#define DMA_CR_HOE_SHIFT                        (4U)
#define DMA_CR_HOE(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

#define DMA_CR_HALT_MASK                        (0x20U)
#define DMA_CR_HALT_SHIFT                       (5U)
#define DMA_CR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

#define DMA_CR_CLM_MASK                         (0x40U)
#define DMA_CR_CLM_SHIFT                        (6U)
#define DMA_CR_CLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

#define DMA_CR_EMLM_MASK                        (0x80U)
#define DMA_CR_EMLM_SHIFT                       (7U)
#define DMA_CR_EMLM(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

#define DMA_CR_ECX_MASK                         (0x10000U)
#define DMA_CR_ECX_SHIFT                        (16U) 
#define DMA_CR_ECX(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

#define DMA_CR_CX_MASK                          (0x20000U)
#define DMA_CR_CX_SHIFT                         (17U)
#define DMA_CR_CX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

/* DMA ESR */
/* Read only*/
#define DMA_ESR_DBE_MASK                        (0x1U)
#define DMA_ESR_DBE_SHIFT                       (0U)

#define DMA_ESR_SBE_MASK                        (0x2U)
#define DMA_ESR_SBE_SHIFT                       (1U)

#define DMA_ESR_SGE_MASK                        (0x4U)
#define DMA_ESR_SGE_SHIFT                       (2U)

#define DMA_ESR_NCE_MASK                        (0x8U)
#define DMA_ESR_NCE_SHIFT                       (3U)

#define DMA_ESR_DOE_MASK                        (0x10U)
#define DMA_ESR_DOE_SHIFT                       (4U)

#define DMA_ESR_DAE_MASK                        (0x20U)
#define DMA_ESR_DAE_SHIFT                       (5U)

#define DMA_ESR_SOE_MASK                        (0x40U)
#define DMA_ESR_SOE_SHIFT                       (6U)

#define DMA_ESR_SAE_MASK                        (0x80U)
#define DMA_ESR_SAE_SHIFT                       (7U)

#define DMA_ESR_ERRCHN_MASK                     (0x3F00U)
#define DMA_ESR_ERRCHN_SHIFT                    (8U)

#define DMA_ESR_CPE_MASK                        (0x4000U)
#define DMA_ESR_CPE_SHIFT                       (14U)

#define DMA_ESR_GPE_MASK                        (0x8000U)
#define DMA_ESR_GPE_SHIFT                       (15U)

#define DMA_ESR_VLD_MASK                        (0x80000000U)
#define DMA_ESR_VLD_SHIFT                       (31U)

/* DMA ERQRL */
#define DMA_ERQRL_ERQ0_MARK                     (0x1U)
#define DMA_ERQRL_ERQ0_SHIFT                    (0U)

#define DMA_ERQRL_ERQ1_MARK                     (0x2U)
#define DMA_ERQRL_ERQ1_SHIFT                    (1U)

#define DMA_ERQRL_ERQ2_MARK                     (0x4U)
#define DMA_ERQRL_ERQ2_SHIFT                    (2U)

#define DMA_ERQRL_ERQ3_MARK                     (0x8U)
#define DMA_ERQRL_ERQ3_SHIFT                    (3U)

#define DMA_ERQRL_ERQ4_MARK                     (0x10U)
#define DMA_ERQRL_ERQ4_SHIFT                    (4U)

#define DMA_ERQRL_ERQ5_MARK                     (0x20U)
#define DMA_ERQRL_ERQ5_SHIFT                    (5U)

#define DMA_ERQRL_ERQ6_MARK                     (0x40U)
#define DMA_ERQRL_ERQ6_SHIFT                    (6U)

#define DMA_ERQRL_ERQ7_MARK                     (0x80U)
#define DMA_ERQRL_ERQ7_SHIFT                    (7U)

#define DMA_ERQRL_ERQ8_MARK                     (0x100U)
#define DMA_ERQRL_ERQ8_SHIFT                    (8U)

#define DMA_ERQRL_ERQ9_MARK                     (0x200U)
#define DMA_ERQRL_ERQ9_SHIFT                    (9U)

#define DMA_ERQRL_ERQ10_MARK                    (0x400U)
#define DMA_ERQRL_ERQ10_SHIFT                   (10U)

#define DMA_ERQRL_ERQ11_MARK                    (0x800U)
#define DMA_ERQRL_ERQ11_SHIFT                   (11U)

#define DMA_ERQRL_ERQ12_MARK                    (0x1000U)
#define DMA_ERQRL_ERQ12_SHIFT                   (12U)

#define DMA_ERQRL_ERQ13_MARK                    (0x2000U)
#define DMA_ERQRL_ERQ13_SHIFT                   (13U)

#define DMA_ERQRL_ERQ14_MARK                    (0x4000U)
#define DMA_ERQRL_ERQ14_SHIFT                   (14U)

#define DMA_ERQRL_ERQ15_MARK                    (0x8000U)
#define DMA_ERQRL_ERQ15_SHIFT                   (15U)

/* DMA EEIRL */
#define DMA_EEIRL_EEI0_MARK                    (0x1U)
#define DMA_EEIRL_EEI0_SHIFT                   (0U)

#define DMA_EEIRL_EEI1_MARK                    (0x2U)
#define DMA_EEIRL_EEI1_SHIFT                   (1U)

#define DMA_EEIRL_EEI2_MARK                    (0x4U)
#define DMA_EEIRL_EEI2_SHIFT                   (2U)

#define DMA_EEIRL_EEI3_MARK                    (0x8U)
#define DMA_EEIRL_EEI3_SHIFT                   (3U)

#define DMA_EEIRL_EEI4_MARK                    (0x10U)
#define DMA_EEIRL_EEI4_SHIFT                   (4U)

#define DMA_EEIRL_EEI5_MARK                    (0x20U)
#define DMA_EEIRL_EEI5_SHIFT                   (5U)

#define DMA_EEIRL_EEI6_MARK                    (0x40U)
#define DMA_EEIRL_EEI6_SHIFT                   (6U)

#define DMA_EEIRL_EEI7_MARK                    (0x80U)
#define DMA_EEIRL_EEI7_SHIFT                   (7U)

#define DMA_EEIRL_EEI8_MARK                    (0x100U)
#define DMA_EEIRL_EEI8_SHIFT                   (8U)

#define DMA_EEIRL_EEI9_MARK                    (0x200U)
#define DMA_EEIRL_EEI9_SHIFT                   (9U)

#define DMA_EEIRL_EEI10_MARK                   (0x400U)
#define DMA_EEIRL_EEI10_SHIFT                  (10U)

#define DMA_EEIRL_EEI11_MARK                   (0x800U)
#define DMA_EEIRL_EEI11_SHIFT                  (11U)

#define DMA_EEIRL_EEI12_MARK                   (0x1000U)
#define DMA_EEIRL_EEI12_SHIFT                  (12U)

#define DMA_EEIRL_EEI13_MARK                   (0x2000U)
#define DMA_EEIRL_EEI13_SHIFT                  (13U)

#define DMA_EEIRL_EEI14_MARK                   (0x4000U)
#define DMA_EEIRL_EEI14_SHIFT                  (14U)

#define DMA_EEIRL_EEI15_MARK                   (0x8000U)
#define DMA_EEIRL_EEI15_SHIFT                  (15U)

/* DMA IRQRL */
#define DMA_IRQRL_INT0_MARK                    (0x1U)
#define DMA_IRQRL_INT0_SHIFT                   (0U)

#define DMA_IRQRL_INT1_MARK                    (0x2U)
#define DMA_IRQRL_INT1_SHIFT                   (1U)

#define DMA_IRQRL_INT2_MARK                    (0x4U)
#define DMA_IRQRL_INT2_SHIFT                   (2U)

#define DMA_IRQRL_INT3_MARK                    (0x8U)
#define DMA_IRQRL_INT3_SHIFT                   (3U)

#define DMA_IRQRL_INT4_MARK                    (0x10U)
#define DMA_IRQRL_INT4_SHIFT                   (4U)

#define DMA_IRQRL_INT5_MARK                    (0x20U)
#define DMA_IRQRL_INT5_SHIFT                   (5U)

#define DMA_IRQRL_INT6_MARK                    (0x40U)
#define DMA_IRQRL_INT6_SHIFT                   (6U)

#define DMA_IRQRL_INT7_MARK                    (0x80U)
#define DMA_IRQRL_INT7_SHIFT                   (7U)

#define DMA_IRQRL_INT8_MARK                    (0x100U)
#define DMA_IRQRL_INT8_SHIFT                   (8U)

#define DMA_IRQRL_INT9_MARK                    (0x200U)
#define DMA_IRQRL_INT9_SHIFT                   (9U)

#define DMA_IRQRL_INT10_MARK                   (0x400U)
#define DMA_IRQRL_INT10_SHIFT                  (10U)

#define DMA_IRQRL_INT11_MARK                   (0x800U)
#define DMA_IRQRL_INT11_SHIFT                  (11U)

#define DMA_IRQRL_INT12_MARK                   (0x1000U)
#define DMA_IRQRL_INT12_SHIFT                  (12U)

#define DMA_IRQRL_INT13_MARK                   (0x2000U)
#define DMA_IRQRL_INT13_SHIFT                  (13U)

#define DMA_IRQRL_INT14_MARK                   (0x4000U)
#define DMA_IRQRL_INT14_SHIFT                  (14U)

#define DMA_IRQRL_INT15_MARK                   (0x8000U)
#define DMA_IRQRL_INT15_SHIFT                  (15U)

/* DMA ERL */
#define DMA_ERL_ERR0_MARK                    (0x1U)
#define DMA_ERL_ERR0_SHIFT                   (0U)

#define DMA_ERL_ERR1_MARK                    (0x2U)
#define DMA_ERL_ERR1_SHIFT                   (1U)

#define DMA_ERL_ERR2_MARK                    (0x4U)
#define DMA_ERL_ERR2_SHIFT                   (2U)

#define DMA_ERL_ERR3_MARK                    (0x8U)
#define DMA_ERL_ERR3_SHIFT                   (3U)

#define DMA_ERL_ERR4_MARK                    (0x10U)
#define DMA_ERL_ERR4_SHIFT                   (4U)

#define DMA_ERL_ERR5_MARK                    (0x20U)
#define DMA_ERL_ERR5_SHIFT                   (5U)

#define DMA_ERL_ERR6_MARK                    (0x40U)
#define DMA_ERL_ERR6_SHIFT                   (6U)

#define DMA_ERL_ERR7_MARK                    (0x80U)
#define DMA_ERL_ERR7_SHIFT                   (7U)

#define DMA_ERL_ERR8_MARK                    (0x100U)
#define DMA_ERL_ERR8_SHIFT                   (8U)

#define DMA_ERL_ERR9_MARK                    (0x200U)
#define DMA_ERL_ERR9_SHIFT                   (9U)

#define DMA_ERL_ERR10_MARK                   (0x400U)
#define DMA_ERL_ERR10_SHIFT                  (10U)

#define DMA_ERL_ERR11_MARK                   (0x800U)
#define DMA_ERL_ERR11_SHIFT                  (11U)

#define DMA_ERL_ERR12_MARK                   (0x1000U)
#define DMA_ERL_ERR12_SHIFT                  (12U)

#define DMA_ERL_ERR13_MARK                   (0x2000U)
#define DMA_ERL_ERR13_SHIFT                  (13U)

#define DMA_ERL_ERR14_MARK                   (0x4000U)
#define DMA_ERL_ERR14_SHIFT                  (14U)

#define DMA_ERL_ERR15_MARK                   (0x8000U)
#define DMA_ERL_ERR15_SHIFT                  (15U)

/* DMA HRSL */
#define DMA_HRSL_HRS0_MARK                    (0x1U)
#define DMA_HRSL_HRS0_SHIFT                   (0U)

#define DMA_HRSL_HRS1_MARK                    (0x2U)
#define DMA_HRSL_HRS1_SHIFT                   (1U)

#define DMA_HRSL_HRS2_MARK                    (0x4U)
#define DMA_HRSL_HRS2_SHIFT                   (2U)

#define DMA_HRSL_HRS3_MARK                    (0x8U)
#define DMA_HRSL_HRS3_SHIFT                   (3U)

#define DMA_HRSL_HRS4_MARK                    (0x10U)
#define DMA_HRSL_HRS4_SHIFT                   (4U)

#define DMA_HRSL_HRS5_MARK                    (0x20U)
#define DMA_HRSL_HRS5_SHIFT                   (5U)

#define DMA_HRSL_HRS6_MARK                    (0x40U)
#define DMA_HRSL_HRS6_SHIFT                   (6U)

#define DMA_HRSL_HRS7_MARK                    (0x80U)
#define DMA_HRSL_HRS7_SHIFT                   (7U)

#define DMA_HRSL_HRS8_MARK                    (0x100U)
#define DMA_HRSL_HRS8_SHIFT                   (8U)

#define DMA_HRSL_HRS9_MARK                    (0x200U)
#define DMA_HRSL_HRS9_SHIFT                   (9U)

#define DMA_HRSL_HRS10_MARK                   (0x400U)
#define DMA_HRSL_HRS10_SHIFT                  (10U)

#define DMA_HRSL_HRS11_MARK                   (0x800U)
#define DMA_HRSL_HRS11_SHIFT                  (11U)

#define DMA_HRSL_HRS12_MARK                   (0x1000U)
#define DMA_HRSL_HRS12_SHIFT                  (12U)

#define DMA_HRSL_HRS13_MARK                   (0x2000U)
#define DMA_HRSL_HRS13_SHIFT                  (13U)

#define DMA_HRSL_HRS14_MARK                   (0x4000U)
#define DMA_HRSL_HRS14_SHIFT                  (14U)

#define DMA_HRSL_HRS15_MARK                   (0x8000U)
#define DMA_HRSL_HRS15_SHIFT                  (15U)

/* DMA CPR */
#define DMA_CPR_CHPRI_MARK                    (0xFU)
#define DMA_CPR_CHPRI_SHIFT                   (0U)
#define DMA_CPR_CHPRI(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_CPR_CHPRI_SHIFT)) & DMA_CPR_CHPRI_MARK)

#define DMA_CPR_DPA_MARK                      (0x40U)
#define DMA_CPR_DPA_SHIFT                     (6U)
#define DMA_CPR_DPA(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CPR_DPA_SHIFT)) & DMA_CPR_DPA_MARK)

#define DMA_CPR_ECP_MARK                      (0x80U)
#define DMA_CPR_ECP_SHIFT                     (7U)
#define DMA_CPR_ECP(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CPR_ECP_SHIFT)) & DMA_CPR_ECP_MARK)


/* DMA TCD SADDR*/
#define DMA_TCD_SADDR_MARK                    (0xFFFFFFFFUL)
#define DMA_TCD_SADDR_SHIFT                   (0U)
#define DMA_TCD_SADDR(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SHIFT)) & DMA_TCD_SADDR_MARK)

/* DMA TCD SOFF*/
#define DMA_TCD_SOFF_MARK                    (0xFFFFU)
#define DMA_TCD_SOFF_SHIFT                   (0U)
#define DMA_TCD_SOFF(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SOFF_SHIFT)) & DMA_TCD_SOFF_MARK)

/* DMA TCD TA*/
#define DMA_TCD_TA_DSIZE_MARK                (0x7U)
#define DMA_TCD_TA_DSIZE_SHIFT               (0U)
#define DMA_TCD_TA_DSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TA_DSIZE_SHIFT)) & DMA_TCD_TA_DSIZE_MARK)

#define DMA_TCD_TA_DMOD_MARK                 (0xF8U)
#define DMA_TCD_TA_DMOD_SHIFT                (3U)
#define DMA_TCD_TA_DMOD(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TA_DMOD_SHIFT)) & DMA_TCD_TA_DMOD_MARK)

#define DMA_TCD_TA_SSIZE_MARK                (0x700U)
#define DMA_TCD_TA_SSIZE_SHIFT               (8U)
#define DMA_TCD_TA_SSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TA_SSIZE_SHIFT)) & DMA_TCD_TA_SSIZE_MARK)

#define DMA_TCD_TA_SMOD_MARK                 (0xF800U)
#define DMA_TCD_TA_SMOD_SHIFT                (11U)
#define DMA_TCD_TA_SMOD(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TA_SMOD_SHIFT)) & DMA_TCD_TA_SMOD_MARK)

/* DMA TCD NBYTES_32bit*/
#define DMA_TCD_NBYTES_32bit_MARK                (0xFFFFFFFFU)
#define DMA_TCD_NBYTES_32bit_SHIFT               (0U)
#define DMA_TCD_NBYTES_32bit(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_32bit_SHIFT)) & DMA_TCD_NBYTES_32bit_MARK)

/* DMA TCD NBYTES_30bit*/
#define DMA_TCD_NBYTES_30bit_MARK                (0x3FFFFFFFU)
#define DMA_TCD_NBYTES_30bit_SHIFT               (0U)
#define DMA_TCD_NBYTES_30bit(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_30bit_SHIFT)) & DMA_TCD_NBYTES_30bit_MARK)

#define DMA_TCD_NBYTES_30bit_DMLOE_MARK          (0x40000000U)
#define DMA_TCD_NBYTES_30bit_DMLOE_SHIFT         (30U)
#define DMA_TCD_NBYTES_30bit_DMLOE(x)            (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_30bit_DMLOE_SHIFT)) & DMA_TCD_NBYTES_30bit_DMLOE_MARK)

#define DMA_TCD_NBYTES_30bit_SMLOE_MARK          (0x80000000U)
#define DMA_TCD_NBYTES_30bit_SMLOE_SHIFT         (31U)
#define DMA_TCD_NBYTES_30bit_SMLOE(x)            (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_30bit_SMLOE_SHIFT)) & DMA_TCD_NBYTES_30bit_SMLOE_MARK)

/* DMA TCD NBYTES_10bit*/
#define DMA_TCD_NBYTES_10bit_MARK                (0x3FFU)
#define DMA_TCD_NBYTES_10bit_SHIFT               (0U)
#define DMA_TCD_NBYTES_10bit(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_10bit_SHIFT)) & DMA_TCD_NBYTES_10bit_MARK)

#define DMA_TCD_NBYTES_10bit_MLOFF_MARK          (0x3FFFFC00U)
#define DMA_TCD_NBYTES_10bit_MLOFF_SHIFT         (10U)
#define DMA_TCD_NBYTES_10bit_MLOFF(x)            (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_10bit_MLOFF_SHIFT)) & DMA_TCD_NBYTES_10bit_MLOFF_MARK)

#define DMA_TCD_NBYTES_10bit_DMLOE_MARK          (0x40000000U)
#define DMA_TCD_NBYTES_10bit_DMLOE_SHIFT         (30U)
#define DMA_TCD_NBYTES_10bit_DMLOE(x)            (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_10bit_DMLOE_SHIFT)) & DMA_TCD_NBYTES_10bit_DMLOE_MARK)

#define DMA_TCD_NBYTES_10bit_SMLOE_MARK          (0x80000000U)
#define DMA_TCD_NBYTES_10bit_SMLOE_SHIFT         (31U)
#define DMA_TCD_NBYTES_10bit_SMLOE(x)            (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_10bit_SMLOE_SHIFT)) & DMA_TCD_NBYTES_10bit_SMLOE_MARK)

/* DMA TCD SLAST*/
#define DMA_TCD_SLAST_MARK                (0xFFFFFFFFU)
#define DMA_TCD_SLAST_SHIFT               (0U)
#define DMA_TCD_SLAST(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SHIFT)) & DMA_TCD_SLAST_MARK)

/* DMA TCD DADDR*/
#define DMA_TCD_DADDR_MARK                (0xFFFFFFFFU)
#define DMA_TCD_DADDR_SHIFT               (0U)
#define DMA_TCD_DADDR(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_SHIFT)) & DMA_TCD_DADDR_MARK)

/* DMA TCD DOFF*/
#define DMA_TCD_DOFF_MARK                 (0xFFFFU)
#define DMA_TCD_DOFF_SHIFT                (0U)
#define DMA_TCD_DOFF(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DOFF_SHIFT)) & DMA_TCD_DOFF_MARK)

/* DMA TCD CITER_LINK_OFF*/
#define DMA_TCD_CITER_LINK_OFF_CITER_MARK                 (0x7FFFU)
#define DMA_TCD_CITER_LINK_OFF_CITER_SHIFT                (0U)
#define DMA_TCD_CITER_LINK_OFF_CITER(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CITER_LINK_OFF_CITER_SHIFT)) & DMA_TCD_CITER_LINK_OFF_CITER_MARK)

#define DMA_TCD_CITER_LINK_OFF_ELINK_MARK                 (0x8000U)
#define DMA_TCD_CITER_LINK_OFF_ELINK_SHIFT                (15U)
#define DMA_TCD_CITER_LINK_OFF_ELINK(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CITER_LINK_OFF_ELINK_SHIFT)) & DMA_TCD_CITER_LINK_OFF_ELINK_MARK)

/* DMA TCD CITER_LINK_ON*/
#define DMA_TCD_CITER_LINK_ON_CITER_MARK                 (0x1FFU)
#define DMA_TCD_CITER_LINK_ON_CITER_SHIFT                (0U)
#define DMA_TCD_CITER_LINK_ON_CITER(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CITER_LINK_ON_CITER_SHIFT)) & DMA_TCD_CITER_LINK_ON_CITER_MARK)

#define DMA_TCD_CITER_LINK_ON_LINKCH_MARK                 (0x7E00U)
#define DMA_TCD_CITER_LINK_ON_LINKCH_SHIFT                (9U)
#define DMA_TCD_CITER_LINK_ON_LINKCH(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CITER_LINK_ON_LINKCH_SHIFT)) & DMA_TCD_CITER_LINK_ON_LINKCH_MARK)


#define DMA_TCD_CITER_LINK_ON_ELINK_MARK                 (0x8000U)
#define DMA_TCD_CITER_LINK_ON_ELINK_SHIFT                (15U)
#define DMA_TCD_CITER_LINK_ON_ELINK(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CITER_LINK_ON_ELINK_SHIFT)) & DMA_TCD_CITER_LINK_ON_ELINK_MARK)

/* DMA TCD DLAST_SGA*/
#define DMA_TCD_DLAST_SGA_MARK                          (0xFFFFFFFFU)
#define DMA_TCD_DLAST_SGA_SHIFT                         (0U)
#define DMA_TCD_DLAST_SGA(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_MARK)

/* DMA TCD CONTROL_STATUS*/
#define DMA_TCD_CONTROL_STATUS_START_MARK               (0x1U)
#define DMA_TCD_CONTROL_STATUS_START_SHIFT              (0U)
#define DMA_TCD_CONTROL_STATUS_START(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_START_SHIFT)) & DMA_TCD_CONTROL_STATUS_START_MARK)

#define DMA_TCD_CONTROL_STATUS_INTMAJ_MARK               (0x2U)
#define DMA_TCD_CONTROL_STATUS_INTMAJ_SHIFT              (1U)
#define DMA_TCD_CONTROL_STATUS_INTMAJ(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_INTMAJ_SHIFT)) & DMA_TCD_CONTROL_STATUS_INTMAJ_MARK)

#define DMA_TCD_CONTROL_STATUS_INTHALF_MARK               (0x4U)
#define DMA_TCD_CONTROL_STATUS_INTHALF_SHIFT              (2U)
#define DMA_TCD_CONTROL_STATUS_INTHALF(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_INTHALF_SHIFT)) & DMA_TCD_CONTROL_STATUS_INTHALF_MARK)

#define DMA_TCD_CONTROL_STATUS_DREQ_MARK                (0x8U)
#define DMA_TCD_CONTROL_STATUS_DREQ_SHIFT               (3U)
#define DMA_TCD_CONTROL_STATUS_DREQ(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_DREQ_SHIFT)) & DMA_TCD_CONTROL_STATUS_DREQ_MARK)

#define DMA_TCD_CONTROL_STATUS_ESG_MARK                (0x10U)
#define DMA_TCD_CONTROL_STATUS_ESG_SHIFT               (4U)
#define DMA_TCD_CONTROL_STATUS_ESG(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_ESG_SHIFT)) & DMA_TCD_CONTROL_STATUS_ESG_MARK)

#define DMA_TCD_CONTROL_STATUS_MAJORLINK_MARK             (0x20U)
#define DMA_TCD_CONTROL_STATUS_MAJORLINK_SHIFT            (5U)
#define DMA_TCD_CONTROL_STATUS_MAJORLINK(x)               (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_MAJORLINK_SHIFT)) & DMA_TCD_CONTROL_STATUS_MAJORLINK_MARK)

#define DMA_TCD_CONTROL_STATUS_ACTIVE_MARK                (0x40U)
#define DMA_TCD_CONTROL_STATUS_ACTIVE_SHIFT               (6U)

#define DMA_TCD_CONTROL_STATUS_DONE_MARK                (0x80U)
#define DMA_TCD_CONTROL_STATUS_DONE_SHIFT               (7U)
#define DMA_TCD_CONTROL_STATUS_DONE(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_DONE_SHIFT)) & DMA_TCD_CONTROL_STATUS_DONE_MARK)

#define DMA_TCD_CONTROL_STATUS_LINKCH_MARK                (0x3F00U)
#define DMA_TCD_CONTROL_STATUS_LINKCH_SHIFT               (8U)
#define DMA_TCD_CONTROL_STATUS_LINKCH(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_LINKCH_SHIFT)) & DMA_TCD_CONTROL_STATUS_LINKCH_MARK)

#define DMA_TCD_CONTROL_STATUS_BWC_MARK                (0xC000U)
#define DMA_TCD_CONTROL_STATUS_BWC_SHIFT               (14U)
#define DMA_TCD_CONTROL_STATUS_BWC(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CONTROL_STATUS_BWC_SHIFT)) & DMA_TCD_CONTROL_STATUS_BWC_MARK)

/* DMA TCD BITER_LINK_OFF*/
#define DMA_TCD_BITER_LINK_OFF_BITER_MARK                 (0x7FFFU)
#define DMA_TCD_BITER_LINK_OFF_BITER_SHIFT                (0U)
#define DMA_TCD_BITER_LINK_OFF_BITER(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_BITER_LINK_OFF_BITER_SHIFT)) & DMA_TCD_BITER_LINK_OFF_BITER_MARK)

#define DMA_TCD_BITER_LINK_OFF_ELINK_MARK                 (0x8000U)
#define DMA_TCD_BITER_LINK_OFF_ELINK_SHIFT                (15U)
#define DMA_TCD_BITER_LINK_OFF_ELINK(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_BITER_LINK_OFF_ELINK_SHIFT)) & DMA_TCD_BITER_LINK_OFF_ELINK_MARK)

/* DMA TCD BITER_LINK_ON*/
#define DMA_TCD_BITER_LINK_ON_BITER_MARK                 (0x1FFU)
#define DMA_TCD_BITER_LINK_ON_BITER_SHIFT                (0U)
#define DMA_TCD_BITER_LINK_ON_BITER(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_BITER_LINK_ON_BITER_SHIFT)) & DMA_TCD_BITER_LINK_ON_BITER_MARK)

#define DMA_TCD_BITER_LINK_ON_LINKCH_MARK                 (0x7E00U)
#define DMA_TCD_BITER_LINK_ON_LINKCH_SHIFT                (9U)
#define DMA_TCD_BITER_LINK_ON_LINKCH(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_BITER_LINK_ON_LINKCH_SHIFT)) & DMA_TCD_BITER_LINK_ON_LINKCH_MARK)


#define DMA_TCD_BITER_LINK_ON_ELINK_MARK                 (0x8000U)
#define DMA_TCD_BITER_LINK_ON_ELINK_SHIFT                (15U)
#define DMA_TCD_BITER_LINK_ON_ELINK(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_TCD_BITER_LINK_ON_ELINK_SHIFT)) & DMA_TCD_BITER_LINK_ON_ELINK_MARK)


/* DMA Hardware Request Allocation */
#define DMA_ADC_Channel      (DMA_TCD_00)
#define DMA_QSPI0_RX_Channel (DMA_TCD_01)
#define DMA_QSPI0_TX_Channel (DMA_TCD_02)
#define DMA_QSPI1_RX_Channel (DMA_TCD_03)
#define DMA_QSPI1_TX_Channel (DMA_TCD_04)
#define DMA_QSPI2_RX_Channel (DMA_TCD_05)
#define DMA_QSPI2_TX_Channel (DMA_TCD_06)
#define DMA_PIT1_Channel     (DMA_TCD_07)
#define DMA_PIT2_Channel     (DMA_TCD_08)
#define DMA_PIT3_Channel     (DMA_TCD_09)
#define DMA_SCI0_TX_Channel  (DMA_TCD_10)
#define DMA_SCI0_RX_Channel  (DMA_TCD_11)
#define DMA_SCI1_TX_Channel  (DMA_TCD_12)
#define DMA_SCI1_RX_Channel  (DMA_TCD_13)
#define DMA_SCI2_TX_Channel  (DMA_TCD_14)
#define DMA_SCI2_RX_Channel  (DMA_TCD_15)




/**
 * @brief: DMA Data Transfer Size Enumeration
 */
typedef enum
{
    DMA_DataSize_8bit  = 0U, /*!< Source/Destination data transfer size is 1 byte every time*/
    DMA_DataSize_16bit = 1U, /*!< Source/Destination data transfer size is 2 byte every time*/
    DMA_DataSize_32bit = 2U, /*!< Source/Destination data transfer size is 4 byte every time*/

} dma_datasize_te;

/**
 * @brief: DMA Address Modulo Enumeration
 */
typedef enum
{
    DMA_MOD_Disable     = 0U,    /*!< Disable modulo */
    DMA_MOD_2byte       = 1U,    /*!< Circular buffer size is 2 bytes */  
    DMA_MOD_4byte       = 2U,    /*!< Circular buffer size is 4 bytes */
    DMA_MOD_8byte       = 3U,    /*!< Circular buffer size is 8 bytes */
    DMA_MOD_16byte      = 4U,    /*!< Circular buffer size is 16 bytes */
    DMA_MOD_32byte      = 5U,    /*!< Circular buffer size is 32 bytes */
    DMA_MOD_64byte      = 6U,    /*!< Circular buffer size is 64 bytes */
    DMA_MOD_128byte     = 7U,    /*!< Circular buffer size is 128 bytes */
    DMA_MOD_256byte     = 8U,    /*!< Circular buffer size is 256 bytes */
    DMA_MOD_512byte     = 9U,    /*!< Circular buffer size is 512 bytes */
    DMA_MOD_1Kbyte      = 10U,   /*!< Circular buffer size is 1K bytes */
    DMA_MOD_2Kbyte      = 11U,   /*!< Circular buffer size is 2K bytes */
    DMA_MOD_4Kbyte      = 12U,   /*!< Circular buffer size is 4k bytes */
    DMA_MOD_8Kbyte      = 13U,   /*!< Circular buffer size is 8k bytes */
    DMA_MOD_16Kbyte     = 14U,   /*!< Circular buffer size is 16k bytes */
    DMA_MOD_32Kbyte     = 15U,   /*!< Circular buffer size is 32k bytes */
    DMA_MOD_64Kbyte     = 16U,   /*!< Circular buffer size is 64k bytes */
    DMA_MOD_128Kbyte    = 17U,   /*!< Circular buffer size is 128k bytes */
    DMA_MOD_256Kbyte    = 18U,   /*!< Circular buffer size is 256k bytes */
    DMA_MOD_512Kbyte    = 19U,   /*!< Circular buffer size is 512k bytes */
    DMA_MOD_1Mbyte      = 20U,   /*!< Circular buffer size is 1M bytes */
    DMA_MOD_2Mbyte      = 21U,   /*!< Circular buffer size is 2M bytes */
    DMA_MOD_4Mbyte      = 22U,   /*!< Circular buffer size is 4M bytes */
    DMA_MOD_8Mbyte      = 23U,   /*!< Circular buffer size is 8M bytes */
    DMA_MOD_16Mbyte     = 24U,   /*!< Circular buffer size is 16M bytes */
    DMA_MOD_32Mbyte     = 25U,   /*!< Circular buffer size is 32M bytes */
    DMA_MOD_64Mbyte     = 26U,   /*!< Circular buffer size is 64M bytes */
    DMA_MOD_128Mbyte    = 27U,   /*!< Circular buffer size is 128M bytes */
    DMA_MOD_256Mbyte    = 28U,   /*!< Circular buffer size is 256M bytes */
    DMA_MOD_512Mbyte    = 29U,   /*!< Circular buffer size is 512M bytes */
    DMA_MOD_1Gbyte      = 30U,   /*!< Circular buffer size is 1G bytes */
    DMA_MOD_2Gbyte      = 31U    /*!< Circular buffer size is 2G bytes */
} dma_addressmod_te;

/**
 * @brief: DMA Channel Preemption Enumeration
 */
typedef enum
{
    DMA_ch_cannot_be_suspended = 0, /*!< channel cannot be suspended by other channel with higher priority */
    DMA_ch_can_be_suspended    = 1, /*!< channel can be suspended by other channel with higher priority */
} dma_ch_preemption_te;

/**
 * @brief: DMA Channel Preempt Ability Enumeration
 */
typedef enum
{
    DMA_ch_can_suspend    = 0,  /*!< channel can suspend other channel with low priority */
    DMA_ch_cannot_suspend = 1,  /*!< channel cannot suspend any channel */
} dma_ch_preempt_ability_te;

/**
 * @brief: DMA Engine Stalls Enumeration
 */
typedef enum
{
    DMA_EngineStalls_None    = 0U, /*!< No DMA engine stalls*/
    DMA_EngineStalls_4cycles = 2U, /*!< DMA engine stalls for 4 cycles after each read/write */
    DMA_EngineStalls_8cycles = 3U  /*!< DMA engine stalls for 8 cycles after each read/write */
} dma_enginestalls_te;

/**
 * @brief: DMA Interrupt Type Enumeration
 */
typedef enum
{
    DMA_Error_Interrupt = 0U,  /*!< Error Interrupt */
    DMA_Half_Interrupt  = 1U,  /*!< Half Interrupt */
    DMA_Major_Interrupt = 2U   /*!< Major Interrupt */
}
dma_interrupt_type_te;

/**
 * @brief: DMA Control Configuration Structure Definition
 */
typedef struct
{
    // DMA Control
    FunctionState debug;                           /*!< Enable Debug */
    FunctionState round_robin_channel_arbitration; /*!< Enable Round Robin Channel Arbitration */
    FunctionState round_robin_group_arbitration;   /*!< Enable Round Robin Group Arbitration */
    FunctionState halt_on_error;                   /*!< Halt On Error */
    FunctionState halt_dma;                        /*!< Halt DMA Operations */
    FunctionState minor_continuous_link;           /*!< Minor Continuous Link Mode */
    FunctionState minor_loop_mapping;              /*!< Enable Minor Loop Mapping */
    
} dma_control_config_ts;

/**
 * @brief: DMA TCD Configuration Structure Definition
 */
typedef struct 
{
    /* Source part */
    uint32_t source;                            /*!< Source Address */
    dma_datasize_te source_datasize;            /*!< Source Data Transfer Size */
    int16_t source_offset;                      /*!< Source Address Offset After Each Access BUS */
    dma_addressmod_te source_modulo;            /*!< Source Address Modulo */    
    FunctionState source_mloe;                  /*!< Source Minor Loop Offset Enable */
    int32_t source_last_address_adjustment;     /*!< Last Source Address Adjustment */

    /* Destin part */
    uint32_t destin;                            /*!< Destin Address */
    dma_datasize_te destin_datasize;            /*!< Destin Data Transfer Size */
    int16_t destin_offset;                      /*!< Destin Address Offset After Each Access BUS */
    dma_addressmod_te destin_modulo;            /*!< Destin Address Modulo */
    FunctionState destin_mloe;                  /*!< Destin Minor Loop Offset Enable */
    int32_t destin_last_address_adjustment;     /*!< Last Destin Address Adjustment */

    /* Other */
    int32_t minor_loop_offset;                  /*!< Address Offset After Minor Loop Complete */
    uint32_t minor_transfer_num;                /*!< Minor Loop Each Transfer Data Size*/
    uint16_t major_loop_num;                    /*!< Number Of Minor Loop Cycles */

    /* Link */
    FunctionState minor_link;                   /*!< Minor Link State */
    uint8_t minor_link_channel;                 /*!< Minor Link Channel */
    FunctionState major_link;                   /*!< Major Link State */
    uint8_t major_link_channel;                 /*!< Major Link Channel */

    /* E_SG */
    uint32_t e_sg_tcd_point;                    /*!< If Enable Scatter-Gather,this value is next TCD address */

    /* Channel Configuration */
    dma_enginestalls_te bwc;                    /*!< Bandwidth Control */
    FunctionState e_sg;                         /*!< Scatter-Gather */
    FunctionState d_req;                        /*!< Disable Hardware Qequest */
    FunctionState interrupt_half;               /*!< Half Major Interrupt */
    FunctionState interrupt_major;              /*!< Major Interrupt */
    
}dma_tcd_config_ts;


/**
 * @brief: DMA Channel Priority Structure Definition
 */
typedef struct
{
    uint64_t ch0  : 4;  /*!< Channel 0 Priority */
    uint64_t ch1  : 4;  /*!< Channel 1 Priority */
    uint64_t ch2  : 4;  /*!< Channel 2 Priority */
    uint64_t ch3  : 4;  /*!< Channel 3 Priority */
    uint64_t ch4  : 4;  /*!< Channel 4 Priority */
    uint64_t ch5  : 4;  /*!< Channel 5 Priority */
    uint64_t ch6  : 4;  /*!< Channel 6 Priority */
    uint64_t ch7  : 4;  /*!< Channel 7 Priority */
    uint64_t ch8  : 4;  /*!< Channel 8 Priority */
    uint64_t ch9  : 4;  /*!< Channel 9 Priority */
    uint64_t ch10 : 4;  /*!< Channel 10 Priority */
    uint64_t ch11 : 4;  /*!< Channel 11 Priority */
    uint64_t ch12 : 4;  /*!< Channel 12 Priority */
    uint64_t ch13 : 4;  /*!< Channel 13 Priority */
    uint64_t ch14 : 4;  /*!< Channel 14 Priority */
    uint64_t ch15 : 4;  /*!< Channel 15 Priority */

} dma_channel_priority_ts;

/*!<---------------End of Definitions--------------->!*/


/*******************************************************************************
 * APIs
 ******************************************************************************/

/* DMA Control Operation Function */
void DMA_Control_Reset(dma_control_config_ts *config);
void DMA_Control_Init(dma_control_config_ts *config);

/* DMA TCD Operation Function */
void DMA_TCD_Reset(dma_tcd_config_ts *tcd_config);
ResultStatus DMA_TCD_Init(dma_tcd *tcd, dma_tcd_config_ts *tcd_config);
void DMA_Init(dma_tcd * tcd, dma_tcd_config_ts * tcd_config);

/* DMA Channel Hardware Request Function */
void DMA_Channel_Hardware_Request_Enable(dma_tcd *CH);
void DMA_Channel_Hardware_Request_Disable(dma_tcd *ch);

/* DMA Channel Operation Related  Function */
void DMA_Channel_Start(dma_tcd *CH);
void DMA_Channel_Clear_Done(dma_tcd *CH);
FlagStatus DMA_Channel_Check_Donebit(dma_tcd *CH);
FlagStatus DMA_Channel_Check_Activebit(dma_tcd *CH);

/*  DMA Channel Major or Half Interrupt Flag Function */
void DMA_Channel_Clear_InterruptFlag(dma_tcd *CH);
FlagStatus DMA_Channel_Check_Interrupt(dma_tcd *CH);

/* DMA Channel Error Interrupt Function */
void DMA_Channel_Error_Interrupt_Enable(dma_tcd *ch);
void DMA_Channel_Error_Interrupt_Disable(dma_tcd *ch);
FlagStatus DMA_Channel_Check_Error_Interrupt(dma_tcd *ch);
void DMA_Channel_Clear_Error_InterruptFlag(dma_tcd *ch);

// DMA Channel Priority Related Function
ResultStatus DMA_Configuration_Channel_Priority(dma_channel_priority_ts *pri);
void DMA_Configuration_Channel_Preemption(dma_tcd *ch, dma_ch_preemption_te ecp, dma_ch_preempt_ability_te dpa);

/*!<---------------End of APIs--------------->!*/
#endif
/*!<---------------End of _LT168_DMA_H --------------->!*/
